A Browser-Based ASIC Physical Design Environment
Bridge the gap between Verilog simulation and manufacturable silicon. Vplay provides a frictionless, cloud-hosted Electronic Design Automation (EDA) terminal for students and researchers to execute the complete RTL-to-GDSII flow using industry-standard open-source toolchains.
The Objective
Why Vplay Was Built
Learning physical semiconductor design traditionally requires navigating immense friction. Hardware engineering students and researchers lose days configuring bare-metal Linux environments, resolving Docker dependencies, and downloading massive Process Design Kits (PDKs) just to run a single synthesis pipeline.
Vplay was developed to eliminate this infrastructure tax. By abstracting the heavy compute requirements of OpenROAD and Yosys into a scalable cloud backend, Vplay allows users to focus strictly on hardware architecture. The objective is to make iterating on chip floorplans, tuning power delivery networks, and fixing placement rules as accessible as compiling software, ultimately democratizing access to VLSI design.
The 7-Track Architecture
Vplay guides users through a structured curriculum, scaling from fundamental logic to custom silicon implementations.
RTL-to-GDSII Express
A frictionless introduction to the OpenLane flow, executing a complete push-button compilation of a basic logic gate to visualize the final GDSII layout.
Logic Synthesis & Optimization
Focus on Yosys. Learn how Verilog is translated into a gate-level netlist, interpreting gate counts, and optimizing for area versus speed.
Floorplanning & Die Sizing
Master physical dimensions. Users interact directly with configurations like FP_CORE_UTIL and DIE_AREA to resolve real-world layout constraints and Power Delivery Network (PDN) pitch requirements.
Placement & Legalization
Understand how standard cells are physically placed within the core area, learning to debug congestion and density bottlenecks.
Clock Tree Synthesis (CTS)
Explore clock distribution networks, minimizing skew and latency across complex sequential circuits.
Routing & Sign-off
Navigate TritonRoute to connect standard cells across metal layers, passing final Design Rule Checks (DRC) and Layout Versus Schematic (LVS) validations.
Custom Silicon Foundry
The ultimate sandbox. Upload your own custom Verilog architectures—from modular crossbar switches to full RISC-V CPU cores—and synthesize them into production-ready silicon layouts.
What Users Learn
What Users Learn & How They Benefit
Real-World Debugging
Users do not just click a button; they learn to read raw OpenROAD execution logs, identify pitch constraint errors (like PDN-0175), and manually tune their physical design variables to pass strict Sky130 node rules.
Instant Visual Feedback
Instead of waiting hours for a local machine to render results, users receive immediate visual feedback on their chip's power grid, cell density, and routing congestion directly in the browser.
AI-Assisted Troubleshooting
An integrated AI tutor helps decipher complex EDA toolchain logs, guiding users through the physics of chip design and suggesting precise configuration overrides.
The Economy
Platform Liquidity & Access
Vplay operates on a sustainable, credit-based compute economy to balance the intensive server resources required for physical synthesis.
Standard Access
Users receive a daily liquidity of 5 compilation credits. This provides full access to the educational tracks, allowing students to iterate on floorplans and synthesis without financial barriers.
Foundry Access
Designed for power users and researchers executing complex custom RTL. This tier unlocks the Custom Silicon Foundry track and expands daily compilation bandwidth to support heavy, iterative design cycles.
How It Works
The Infrastructure "Tax"
Vplay is built on a robust, asynchronous cloud architecture designed to handle heavy Electronic Design Automation workloads without timing out the client browser.
Frontend
A responsive Next.js and React terminal interface, providing real-time log streaming and interactive GDSII visualization.
Compute Backend
Hosted on dynamic Microsoft Azure virtual machines (scaling via Standard_B2als_v2 and B4ls_v2 instances) to handle high-RAM routing and placement algorithms efficiently.
Authentication & Security
Secured via Firebase authentication, with automated HTTPS certificate management handled by a Caddy reverse proxy.
EDA Toolchain
Fully Dockerized OpenLane 1 flow, integrating Yosys, OpenROAD, Magic, and the SkyWater 130nm PDK.
About the Creator